Intel’s Next-Gen Processors
Over the last year or two, we’ve heard a lot about Intel’s silicon roadmap, processor branding changes, and new production process terminology. Intel will released “Meteor Lake.” chips in September. These chips were probably Intel’s 14th Gen Core CPUs in the past.
Given early briefings’ focus on economy and battery life, Meteor Lake CPUs likely debut in consumer laptops before desktop chips. Intel hasn’t fully committed to this Intel’s Next-Gen Processors. Intel Tech Tour, a series of deep-dive presentations on Meteor Lake for industry and the press, revealed new information about how the upcoming chips are made with new designs, updated technology, and fresh features that will boost performance and efficiency.
Further specifics concerning Meteor Lake chip types, early implementations, and performance are not yet available from Intel. However, the Tech Tour disclosed Meteor Lake insider knowledge. From chip manufacture and design to user capabilities, the Intel’s Next-Gen Processors should be different. Here’s a rundown of the latest, from silicon to beyond.
What’s Meteor Lake? First Intel Core Ultra Chips
Last year, Intel announced a dramatic rebranding of its Core CPUs, removing the generation numbers (12th Gen Core, 13th Gen Core, etc.). Meteor Lake alters more than labels. Intel changed practically everything about the new processors, from the die layout to the architecture, providing features, capabilities, and a path for future innovation.
Meteor Lake additionally modifies manufacturing techniques, adds a “stacked” 3D CPU architecture, and builds on the current tiered high-power vs. low-power processor-core strategy. With everything going on, Intel’s Next-Gen Processors should be reintroduced. This CPU architecture is behind Intel’s first generation of Core Ultra processors, which may eliminate the “i” for simplicity.
Intel 4 Manufacturing: 7nm
Intel’s largest update is to their Intel 4 foundry process. This new 7-nanometer (7nm) manufacturing technique employs extreme ultraviolet (EUV) lithography to make ever-smaller chips, keeping Moore’s Law going with tinier and more transistors per surface area.
Intel claims that their EUV lithography equipment is the most complex ever, but the advantages are clear: improved scalability and power efficiency. Intel 4 should outperform 10nm Intel 7 in performance per watt by 20%.
Also geared for high-performance applications, it supports low- and high-voltage operations, allowing CPUs more flexibility to handle varied activities.
Foveros3D die stacking: monolith gone
Intel’s latest packaging method, Foveros, employs 3D stacking to merge “chiplets” into a chip. Intel’s disaggregated architecture is more configurable than prior approaches that manufactured CPUs as a slab or “monolith.”
Intel can now optimize each CPU element for specialized operations and assemble them into a tiny, efficient 3D stack thanks to the shift away from monolithic architecture. This allows various chip portions to be produced using different processes. Intel can manufacture the central processing portion using its latest approach, use older processes for other sections of the final assembled chip , or outsource portions to other manufacturers.
Also important for process improvement? Instead of “binning” the finished CPU after manufacture, Intel can accurately build CPUs from pre-tested components. Binning sorts completed CPUs by how many components fail the fabricator’s highest criteria for that architecture.
Underperforming components are supplied as “lesser” versions. Binning produces the CPU power tiers, which will likely be called Intel 9, Intel 7, Intel 5, etc. Testing top-tier samples become “9” chips all the way down.
Intel’s new tiled-component approach lets it construct CPUs from proven pieces. This simplifies future feature development since the manufacturer may upgrade individual chip parts without redesigning a “single piece” monolithic CPU.
That sounds wonderful, but the tiles must communicate at blink speed. Die-to-die interconnects micro-wires that connect CPU portions for I/O, power supply, and routing are needed to connect all these tiles. This is where Foveros technology helps. Foveros unites the architecture with high-density, high-bandwidth, low-power interconnects.
AMD has used chiplet designs for years, but Intel’s transition will change how the business produces CPU hardware.
Breaking Down Intel’s Tile Layout and Disaggregated Design
This new tile-based design is disaggregated. Instead of building a single monolithic chip, the CPU may be made from smaller, simpler pieces and integrated onto a base wafer using interconnects to form a chip die. But this Voltron-like method needs many components to operate together.
Meteor Lake will include four tiles for current CPU technologies: compute, graphics, SoC, and I/O.
Most people conceive of the Meteor Lake chip as a traditional CPU. Performance and Efficient cores (P- and E-cores) in the Compute Tile power your system. The most sophisticated tile of the four, it uses 7nm Intel 4.
Intel calls their new P-core microarchitecture “Rosewood Cove.” The E-cores now have “Crestmont.” microarchitecture. Multi-threaded workloads, cache, memory bandwidth, and AI workload acceleration have been improved.
This relies on Thread Director. This software, integrated into previous Intel’s Next-Gen Processors, ensures that processing activities are shifted to the best core at the proper moment. In Meteor Lake, an upgraded Thread Director connects these cores together with better task-scheduling and guidance, shunting less-demanding activities to the E-cores or the new “Low Power E-cores” on the SoC tile for efficiency and power savings.
On-the-fly prioritizing saves P-cores for higher-demand workloads and saves electricity by not spinning up the Compute Tile. For better hardware-software interaction, Intel and Microsoft co-designed the new Thread Director to match Windows 11.
The SoC Tile handles media and display control, Wi-Fi networking, and hardware security. A new, unique zone is also there.
The “Low Power Island” on the SoC Tile has a cluster of efficient processing cores called Low Power E-cores. Optimised for low-lift workloads and background activities, these cores improve efficiency and free up Compute Tile cores for more demanding application tasks.
Because the Low Power Island can be power-managed independently from the higher-performance cores, it reduces CPU power overhead. If a group of jobs doesn’t use the Compute Tile’s P-cores or E-cores, keeping it idle while the Island is active may save electricity.
Intel’s first integrated artificial intelligence engine, a neural processing unit (NPU), runs local, client-side AI models effectively on the SOC Tile. In previous Meteor Lake talks, the NPU was called a “VPU.” The NPU and CPU conduct AI jobs together. Intel placed it on the SoC tile to provide AI high-bandwidth access to other chip parts, improving graphics and Wi-Fi performance.
The SoC Tile houses the memory controller and DDR bus for system memory communication.
The third tile, the Graphics Tile, covers all gaming, content production, and media streaming graphics and computation operations. Intel Arc, another new technology, is seen here. Alchemist Xe LPG’s CPU Graphics Tile utilizes Arc graphics technology.
Intel’s integrated graphics support will improve greatly. Intel will provide integrated graphics beyond Iris Xe on Meteor Lake CPUs, although not all will have Arc-level performance.
Connections, pins, and external signals are handled by this last chip section. USB and storage connectors are typical, but Intel said the new platform supports Thunderbolt 4 and PCI Express Gen 5.
We think Intel included Thunderbolt 5 capability, albeit they didn’t state. Intel said in a Thunderbolt 5 briefing that the new standard will emerge . Intel may not incorporate the new standard on the initial Meteor Lake CPUs. However, Thunderbolt 5 may be referenced again when Meteor Lake machines are unveiled.