Synopsys VCS
Innovative features in Synopsys VCS functional verification enable shift-left verification processes early in the design cycle and excellent performance. Recent product features include Design Intent Verification (DIV) and Dynamic Test Loading (DTL). Synopsys VCS verified OpenCL graphics core raytracing performance in all tests. AMD conducted Tests A and B for this workload.
AMD ran one full copy of Synopsys VCS on one AMD EPYC 9374F CPU core for Test A. All CPUs were evaluated with equivalent to their processor cores in simultaneous jobs. The calculation 32 CPU cores / 1 core per copy = 32 copies shows that a 32-core AMD EPYC 7573X processor ran 32 copies of the full application. The cache capacity of 4th Gen AMD EPYC CPUs with AMD 3D V-Cache technology benefits this workload best.
AMD used different numbers of full copies of Synopsys VCS to test processor performance under different load circumstances in Test B. The number of concurrent jobs ranged from 1 to the processor core count. For instance, each 16-core CPU had 1, 2, 3, 4, 5, 6, 7, 8, 12, and 16 jobs.
These experiments assessed processor performance under increasing workload scenarios that stressed compute cores and L3 cache. In general, more concurrent jobs lowered runtime and increased throughput and energy usage.
Fusion compiler Synopsys
A unified tool for RTL-to-GDSII implementation is Synopsys Fusion Compiler. Advanced optimisation methods, low-power design, and advanced process nodes are supported in this integrated design and implementation environment. Facilitating efficient and high-performance integrated circuit designs is its main goal.
AMD EPYC 9374F Benchmark
AMD tested Synopsys Fusion Compiler’s synthesis, placement, and routing functions to assess AMD EPYC performance in these major application domains.
Synthesis
A Register-Transfer Level (RTL) design model is automatically converted to a gate-level netlist during synthesis. AMD used 8 processing cores per Synopsys Fusion Compiler instance for synthesis. All processors were given a number of simultaneous jobs equal to the total processor cores divided by 8, resulting in 8 cores per copy of the whole application. A 32-core AMD EPYC 75F3 processor executed 4 copies of the full application at once.
AMD EPYC 9654
Synopsys Fusion Compiler synthesised a 664k-instance 5nm GFX SOC in AMD testing. The general-purpose 4th Gen AMD EPYC 9654 CPU had the largest generational uplift for this workload. However, high-frequency 4th Gen AMD EPYC processors performed best for this application at lower core counts.
Placement
Placing electronic components, circuits, and logic parts on the wafer requires precise positioning. AMD ran each Synopsys Fusion Compiler instance for placement on 8 CPU cores. All systems were tested with concurrent jobs equal to the processing cores divided by 8. On a 32-core AMD EPYC 75F3 processor, 4 copies of the full application ran simultaneously.
Synopsys Fusion Compiler was tested for 5nm tile arrangement and optimal clock optimisation for a 664k-instance GFX SOC. The general-purpose 4th Gen AMD EPYC 9654 CPU had the largest generational uplift for this workload. At lower core counts, high-frequency 4th Gen AMD EPYC CPUs performed well for this application.
Routing
Routing determines the wire layout needed to connect all circuit components. AMD ran each Synopsys Fusion Compiler instance on 8 CPU cores for routing. All processors were tested with 8 cores distributed among multiple jobs. On a 32-core AMD EPYC 75F3 processor, 4 copies of the full application ran simultaneously.
Synopsys Fusion Compiler routed a 664k-instance 5nm GFX SOC during testing. General-purpose 4th Gen AMD EPYC 9654 CPU showed the greatest generational gain for this workload. High-frequency 4th Gen AMD EPYC processors favoured lower core counts.
Siemens Calibre nmDRC
Major foundries use Siemens Calibre nmDRC for internal sign-off DRC due to its constant functionality innovation and top performance and capacity. AMD ran 8 processing cores for each Siemens Calibre nmDRC instance, evaluating 8 copies of the application simultaneously. Using a 32-core AMD EPYC 75F3, 4 versions of the application ran simultaneously.
Siemens Calibre nmDRC GFX SoC Tile design were tested for DRC on 165M geometries in a 5nm tile. General-purpose 4th Gen AMD EPYC 9654 CPU showed the greatest generational gain for this workload. High-frequency 4th Gen AMD EPYC processors favoured lower core counts.
RedHawk-SC
Ansys RedHawk-SC is a dependable multiphysics signoff solution for digital architectures that uses “what-if” research to uncover flaws and optimise power and performance. AMD ran each Ansys RedHawk-SC instance on 8 CPU cores. Therefore, all CPUs were tested with a burden equal to the total processing cores divided by 8.
AMD EPYC 75F3 32-Core Processor
Example: A 32-core AMD EPYC 75F3 system ran four copies of the full application. Dynamic IR study of a 5nm GFX SoC with 541K components was done utilising Ansys RedHawk-SC L2 SRAM Array. The 32-core 4th Gen AMD EPYC 9374F CPU had the largest generational uplift for this task.
AMD EPYC 7573X
For large post-layout analogue, RF, SerDes, DRAM, and Flash designs, Synopsys PrimeSim SPICE delivers breakthrough performance. AMD ran each Synopsys PrimeSim SPICE instance on 8 CPU cores. This assessed all processors with concurrent jobs equal to the processor cores divided by 8. A 32-core AMD EPYC 7573X processor ran four parallel instances of the whole application.
The testing involved transient analysis of a 5nm SRAM array with 1.1 million transistors using Synopsys PrimeSim SPICE L2 SRAM Array design. AMD 3D V-Cache technology in 4th Gen AMD EPYC CPUs boosts cache capacity for this workload.
Siemens Tessent
Siemens Tessent Test Solutions provides silicon test and operations applications and IP to address manufacturing test, debug, and yield ramp concerns for today’s most complex SoCs. AMD ran Siemens Tessent on one CPU core. Each processor was tested with a workload equal to its cores. For instance, a 32-core AMD EPYC 7573X system ran 32 copies of the application.
Test patterns were created for a 664K-instance 5nm GFX SOC tile. AMD 3D V-Cache technology in 4th Gen AMD EPYC CPUs boosts cache capacity for this workload.
Formality equality in Synopsys
Equivalence-checking (EC) solution Synopsys Formality uses formal, static methods to determine if two design versions are functionally identical. It supports Engineering Change Orders (ECOs) and enhanced debugging to help users implement and validate them. Formality supports all Design Compiler and Fusion Compiler optimisations, ensuring high-quality, verifiable results.
AMD ran Synopsys Formality Equivalence on two CPU cores per instance. Multiple simultaneous jobs equal to the processing cores divided by 2 tested all processors. A 32-core AMD EPYC 7573X system ran 16 copies of the full application since 32 CPU cores were divided by 2 cores each copy.
A 5nm GFX SOC tile with 664K instances was tested for RTL-gate equivalency. The enlarged cache in 4th Gen AMD EPYC CPUs with AMD 3D V-Cache helped this task.
Cadence SpectreX
Due to its highly distributed workload, Cadence Spectre X Simulator can simulate high-speed and high-capacity tasks. SPICE-accurate simulation, rapid convergence, scalable performance, and a mode for very large system simulations are its strengths.
AMD used 8 processing cores every Cadence Spectre X instance. All processors were tested with a workload of the total processor cores divided by 8, resulting in the number of simultaneous application instances. For instance, a 32-core AMD EPYC 7573X server ran 4 instances of the whole application. Cadence Spectre X testing used affinity (CPU pinning) to pin CPUs on the same NUMA node where possible.
Testing focused on Cadence Spectre X SPICE DDR PLL transient analysis of 1.8 million nodes in a 5nm DDR PLL. AMD 3D V-Cache technology in 4th Gen AMD EPYC CPUs boosted cache for this workload.
Prime Time Suite Synopsys
Prime Time, Prime Time SI, Prime Time ADV, and Prime Time PX are part of Synopsys’ Prime Time signoff solution package, which includes intelligent timing, signal integrity, power, timing constraint, and variation-aware analysis methods. AMD ran one instance of Synopsys Prime Time Suite on all CPU cores. Each CPU used all cores for one job. A 32-core AMD EPYC 75F3 system ran one instance of the application using all 32 CPU cores.
One section of the Large GFX Top-Level design Flat SI arrangement was timed using Synopsys PrimeTime Suite during testing. The 5nm architecture had 181 million leaf cells, ports, hierarchies, and 332 million nets. The high-frequency 32-core 4th Gen AMD EPYC 9374F CPU had the maximum generational uplift for this task.
