In order to satisfy the expectations of artificial intelligence in the future, Intel Foundry’s Technology Research team showcased industry-first developments in transistor and packaging technologies at IEDM 2024.
What’s new in Intel Foundry News
The IEEE International Electron Devices Meeting (IEDM 2024) saw Intel Foundry unveil new advancements that would accelerate the semiconductor industry into the next decade and beyond. By employing subtractive ruthenium, Intel Foundry demonstrated new material innovations that enhance connectivity within a chip and provide capacitance of up to 25%.
In order to facilitate ultra-fast chip-to-chip assembly, Intel Foundry was also the first to report a 100x throughput boost employing a heterogeneous integration approach for advanced packaging. Additionally, Intel Foundry showed work with silicon RibbonFET CMOS and with gate oxide module for scaled 2D FETs for enhanced device performance in order to further promote gate-all-around (GAA) scaling.
Why It Matters
In order to meet the industry’s insatiable demand for more energy-efficient, high-performing, and reasonably priced computing applications like artificial intelligence (AI), advancements in transistor and interconnect scaling, multiplied by future advanced packaging capabilities, are essential as the industry moves toward putting one trillion transistors on a chip by 2030.
The industry will require new materials to enhance Intel Foundry’s Power Via backside power supply to reduce interconnect crowding and allow scalability. This is essential for maintaining Moore’s Law and propelling the semiconductor into new eras for artificial intelligence.
How We’re Approaching It
In order to overcome the expected limits of copper transistors in interconnect scaling for future nodes, enhance current assembly methods, and further define and shape the transistor roadmap for gate-all-around scaling and beyond, Intel Foundry has suggested a number of paths:
Subtractive Ruthenium (Ru)
Intel Foundry demonstrated subtractive ruthenium, a novel important alternative metallization material that leverages thin film resistivity and airgaps to provide a notable improvement in interconnect scaling, in order to enhance the performance and interconnections within devices. Without the need for costly lithographic airgap exclusion zones around vias or self-aligned via flows that require selective etches, the team was the first to demonstrate in R&D test vehicles a feasible, economical, and high-volume manufacturing compatible subtractive Ru integrated process with airgaps.
The advantages of using subtractive Ru as a metallization strategy to substitute copper damascene in tight pitch layers were demonstrated by the implementation of airgaps using subtractive Ru, which resulted in a reduction of up to 25% in line-to-line capacitance at pitches smaller than or equal to 25 nanometers (nm). Future nodes from Intel Foundry may use this solution.
Selective Layer Transfer (SLT)
Intel Foundry is the first to demonstrate Selective Layer Transfer (SLT), a heterogeneous integration solution that enables ultra-thin chiplets with much better flexibility to enable smaller die sizes and higher aspect ratios compared to traditional chip-to-wafer bonding. This technology allows for up to 100x higher throughput for ultra-fast chip-to-chip assembly in advanced packaging. For hybrid or fusion bonding of particular chiplets from one wafer to another, this enables a higher functional density and results in a more adaptable and economical solution. For AI applications, this method provides a more effective and adaptable architecture.
Silicon RibbonFET CMOS
Intel Foundry demonstrated silicon RibbonFET CMOS (complementary metal oxide semiconductor) transistors at a gate length of 6 nm with industry-leading short channel effects and performance at aggressively scaled gate length and channel thickness in an effort to push gate-all-around RibbonFET silicon scaling to its limits. This development opens the door for further gate length scaling, which is one of the fundamental tenets of Moore’s Law.
Gate Oxide for Scaled GAA 2D FETs
Intel Foundry demonstrated their work on the manufacturing of GAA 2D NMOS and PMOS transistors with scaled gate length down to 30 nm, with an emphasis on gate oxide (GOx) module development, in an effort to further accelerate gate-all-around innovation beyond CFET. Two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors, which could eventually replace silicon in sophisticated transistor processes, are being investigated by the industry, according to the study.
The first 300-mm gallium nitride (GaN) technology for power and radio frequency (RF) devices, which can give higher performance and voltages. temperatures than silicon, is another example of how Intel Foundry has advanced research. Made on a 300 mm GaN-on-TRSOI (“trap-rich” silicon-on-insulator) substrate, these are the first high-performance scaled enhancement-mode GaN MOSHEMTs (metal-oxide-semiconductor high electron mobility transistors) in the industry. By lowering signal loss and improving signal linearity, advanced-engineered substrates like GaN-on-TRSOI can perform better in applications like RF and power electronics. This allows for the realization of sophisticated integration schemes through backside substrate processing.
More from IEDM 2024
In order to address the demands of many applications, including artificial intelligence, Intel Foundry also presented its vision for the future of improved packaging and transistor scaling during the conference. To assist propel the next ten years toward more power-efficient AI, three major areas of innovation were highlighted.
- Sophisticated memory integration to remove latency, bandwidth, and capacity constraints.
- Optimizing connectivity bandwidth with hybrid bonding.
- Extension of a modular system with matching connecting options.
A call to action to create important and ground-breaking ideas for ongoing transistor scaling in the trillion-transistor era was also shared by Intel Foundry. According to Intel Foundry, creating a transistor that can operate at ultra-low voltages (less than 300 millivolts) can significantly reduce energy usage and thermal dissipation while also assisting in addressing growing thermal constraints.
What is Intel Foundry?
Intel Foundry is a foundry company that provides complicated systems-of-chips processor design, fabrication, packaging, and testing services:
Services
Intel Foundry provides testing, packaging, and front-end and back-end design services.
Capacity
With facilities in the US, Germany, and Poland, Intel Foundry has a global supply chain and manufacturing capability. Over the next ten years, Intel intends to invest up to $200 billion in capacity.
Technology
Advanced system assembly and test (ASAT) capabilities, specialty node evolutions, and Intel 14A process technology are all provided by Intel Foundry.
Creativity
Multiple architectures, including as ARM, RISC-V, x86, and custom ASICs, are supported by Intel Foundry. Additionally, they collaborate with the ecosystem to promote innovation.
Clients
Microsoft and other clients’ specific product needs are supplied by Intel Foundry.
The purpose of Intel Foundry is to assist clients in achieving their AI goals. They provide a fresh method for supporting full stack solutions in order to shorten time to market.
