Samsung 1.4nm process
In the words of Jeong Gi-Tae, vice president of Samsung Foundry, the organization planned to increase the number of nanosheets from three to four through the development of its SF(1.4nm-class) 1.4nm process technology, as according to the DigiTimes. The modification is anticipated to bring about significant beneficial effects on electrical consumption and performance.
Samsung, with its SF3E (also known as 3nm-class gate-all-around ear, 3GAE) in mid-2022, was the first company to introduce a process technology based on gate-all-around (GAA) nanosheet transistors. The technique is utilized by the corporation to produce a range of chips; nevertheless, it is thought that the node’s application is restricted to little chips, such those that are mined for cryptocurrencies.
Advantages of 1.4nm Process
Samsung intends to launch its SF3 technology, which is expected to find use in a greater number of applications, next year. Samsung’s performance-enhanced SF3P technology, which was created with data center CPUs and GPUs in mind, will be made available in 2025.
Additionally, Samsung plans to launch its SF2 (2nm-class) fabrication method in 2025. This process will utilize backside power supply in addition to GAA transistors, which offers significant advantages in terms of transistor density and power delivery.
Benefits of Samsung’s 1.4nm Process
After the release of GAA-based SF3E, Samsung manufacturing nodes will likely undergo their largest redesign in 2027 when their SF1.4 technology adds a fourth nanosheet, bringing the total number of nanosheets to four.
Enhancing the driving current through an increase in the number of nanosheets per transistor can improve performance. The transistor’s switching ability and operational speed are improved when there are more nanosheets because they let more current to pass through the device. Additionally, more nanosheets may result in improved current flow management, which may lessen leakage current and, ultimately, lower power consumption. Moreover, enhanced regulation of current flow results in less heat generation by the transistors, augmenting power efficiency.
GAA transistors will be used by both Intel and TSMC with their 20A and N2 (2nm-class) process technologies, which are expected to be released in 2024 and 2025, respectively. Samsung will have a great deal of experience with gate-all-around transistors by the time these companies release their nanosheet-based nodes, which could be advantageous for the foundry.
