Intel Agilex 7 FPGA
AI-Based Wireless RAN Timing Synchronisation with Altera Agilex 7 SoC FPGAs
Intelligent holdover and adaptive clock correction on FPGA eliminate GNSS dependence
Today’s Radio Access Networks (RAN) depend on precise timing for both performance and stability. Wireless infrastructure relies on exact frequency and phase alignment for everything from low-latency scheduling and synchronisation across base stations to coordinated multi-point (CoMP) broadcasts.
The GNSS, PTP, and SyncE protocols are typically used to accomplish this synchronisation. However, indoor deployment, jamming, or spoofing systems have to switch to holdover when GNSS signals are disrupted by urban canyon effects, which frequently results in decreased accuracy, increased jitter, and service interruptions.
AI-Enhanced Holdover: Using Machine Learning to Forecast Clock Drift
Using Multilayer Perceptron (MLP) and Long Short-Term Memory (LSTM) neural networks that are taught to identify and forecast clock drift patterns in real time, Altera’s novel method delivers AI-driven timing holdover. The direct deployment of these models onto Agilex 7 SoC FPGAs guarantees ultra-low-latency adaptation in the event of GNSS signal loss.
Through dynamically modifying the Digital Phase-Locked Loop (DPLL) in response to learnt environmental behaviour, this technique:
- keeps frequency synchronisation constant when GNSS is unavailable.
- Up to ten times less power and maintenance is required.
- Adjusts to oscillator drift brought on by ageing, temperature, and voltage
- Guarantees accurate clock correction in real time for next-generation RAN installations.
Built for Resilience in Open and Edge RAN
This solution was created with MATLAB and implemented using Altera’s FPGA AI Suite, Quartus Prime software, and PTP Servo IP. It has been stress-tested across environmental conditions and validated through multi-day drift simulations. It is appropriate for Open RAN, private 5G, and remote edge deployments where GNSS isn’t assured since it provides reliable timing resilience even in less-than-optimal deployment scenarios.
FPGAi: Where Intelligence Counts
FPGAi allows system architects to include intelligence into hardware that can adapt on its own as networks get closer to the edge and timing issues become more complex. This AI-native synchronisation solution is an excellent illustration of how neural inference and programmable logic combine to lower the Total Cost of Ownership (TCO) and increase RAN reliability.
Intel Agilex 7 FPGA and SoC FPGA
For the majority of bandwidth, computation, and memory-intensive applications, the best-performing FPGAs offer industry-leading fabric and IO speeds.
Agilex 7 devices outperform rival 7 nm FPGAs in terms of fabric performance per watt. Also available are 32GB HBM2e, PCI Express (PCIe) 5.0, Compute Express Link (CXL), integrated Arm-based CPUs, and 116Gbps transceivers. These traits make them ideal for broadcast, data centre, networking, industrial, and defence applications.
Agilex 7 FPGA and SoC FPGA F-Series
General-purpose FPGAs based on Intel’s 10 nm SuperFin manufacturing technology are known as F-Series devices. With features including high-performance crypto blocks, powerful digital signal processing (DSP) blocks that enable multiple precisions of fixed-point and floating-point operations, and transceiver rates up to 58 Gbps, they are perfect for a variety of applications across numerous markets.
Agilex 7 FPGA and SoC FPGA I-Series
For applications requiring a lot of bandwidth, the I-Series devices provide the best I/O interfaces. This series, which is based on Intel’s 10 nm SuperFin process technology, expands on the characteristics of the F-Series devices, which include PCIe 5.0 support, cache- and memory-coherent attach to CPUs via Compute Express Link (CXL), and transmission rates of up to 116 Gbps.
Agilex 7 FPGA and SoC FPGA M-Series
Applications requiring a lot of memory and computation are best suited for M-Series devices. The I-Series device features, such as integrated high-bandwidth memory (HBM) with digital signal processing (DSP) and high-efficiency interfaces to DDR5 memory with a hard memory Network-on-Chip (NoC) to maximize memory bandwidth, are expanded upon in this series, which leverages Intel 7 process technology.
| F-Series For wide range of applications that require optimal balance of power and performance. | I-Series For high-performance processor interface and bandwidth-intensive applications. | M-Series For compute-intensive and high-memory-bandwidth applications. |
|---|---|---|
| 573k – 2.7M LEs | 1.9M – 4M LEs | 3.2M – 3.8M LEs |
| Up to 58 G transceivers | Up to 116 G transceivers | Up to 116 G transceivers |
| PCIe 4.0 x16 | PCIe 5.0 x16 | PCIe 5.0 x16 |
| DDR4 interface | DDR4 interface | DDR4, DDR5 and LPDDR5 interfaces |
| Quad-core Arm Cortex-A53 SoC option | Quad-core Arm Cortex-A53 SoC option | Quad-core Arm Cortex-A53 SoC option |
| – | Compute Express Link (CXL) to Intel Xeon Scalable processor | Compute Express Link (CXL) to Intel Xeon Scalable processor |
| – | – | Non-HBM and HBM (16GB, 32GB) support |
Advantages
Core Architecture Provides Benefits for Design Optimisation
Key benefits of the second-generation Intel Hyperflex FPGA Architecture include improved performance, reduced total power consumption, enhanced design capabilities, and higher designer productivity, all of which allow for significant design optimisation.
Boost Performance and Quicken Digital Signal Processing (DSP)
For greater performance/watt in AI and other compute-intensive applications, the first FPGA to enable protected half-precision floating point (FP16) and BFLOAT16 offers up to 38 tera floating point operations per second (TFLOPS) of DSP performance (FP16).
Preserve Integrity and Confidentiality with Sturdy Security Features
Configuration, authentication, bitstream encryption, key protection, tamper sensors, and active tamper detection and response are all managed by the dedicated Secure Device Manager (SDM), which lets you choose the features you need to achieve your security goals.
Applications and Use Cases
Use F-Tiles to Implement Advanced Networking Solutions with Agilex 7 FPGAs
Modern FPGA system-level design relies heavily on advanced silicon and chiplet technologies because they offer scalability and the flexibility of a programmable fabric, while yet delivering the power economy and performance of hardened functions.
Use Agilex 7 FPGAs to Create Effective and Affordable mMIMO Solutions
The number of users and the volume of data that each user generates and consumes are driving an exponential increase in the demand for mobile communications. Mobile network operators (MNOs) are switching to fifth-generation (5G) mobile networks and using high-frequency (HF) radio frequency (RF) bands in order to satisfy these increasing demands.
Agilex 7 FPGAs Aim for 5G Networks, SmartNICs, and IPUs
Cyberattacks and data breaches from the edge to the cloud increase when high-speed networks are attacked. Since cyberattacks and data breaches are becoming more common, encrypted communications have various uses. 5G networks, Open vSwitch (OvS), and network storage.
Key Features
Intel Hyperflex FPGA Architecture of the Second Generation: Bypassable registers known as Hyper-Registers are added by the Intel Hyperflex FPGA architecture and are dispersed across the FPGA fabric. They are accessible at the inputs of every functional block and on each interconnect routing segment.
DSP with Variable-Precision: The novel DSP architecture enables the DSP blocks to be configured to provide multiplication, multiply-add, multiply-accumulate, floating point and integer addition, and variable-precision signal processing.
Interface for DDR4: Hardened memory controllers address memory system bottlenecks in high-performance computing and data centres by providing performance, density, low power, and control.
Arm Cortex-A53 quad-core SoC: An integrated quad-core Arm Cortex-A53 CPU choice that has been hardened.
