Quartus Prime Pro Edition 25.1 with Support for the New Agilex 3 FPGAs is Introduced by Altera
Quartus Prime Pro 25.1, which supports Agilex 3, the newest member of the Agilex family, is now available. With the help of this upgrade, developers may create edge and embedded apps that are high-performing and power-efficient.
Comprehensive Support for Agilex 3 FPGAs
For edge and embedded applications, the Agilex 3 FPGA series offers cost optimisation, high performance, and power economy. The Agilex 3 higher-speed transceivers for enhanced connection, the on-chip dual Cortex-A55 ARM cores for providing potent computing capabilities, and the extended memory support, including LPDDR4, allow you to design, test, and implement solutions more efficiently with this release.
Agilex 3 makes use of Intel’s variable pitch BGA packaging to offer more efficient and compact designs for applications with limited board space. With this technology, developers can retain performance and power economy while packing more functionality into smaller footprints.
In FPGA applications, security is crucial for safeguarding sensitive data and intellectual property. New features in Agilex 3 improve physical security, authentication, and encryption, increasing the resistance of designs to manipulation and attacks.
Improvements to Nios V Soft Processors
In embedded applications, the Nios V is essential, and this edition offers efficiency and performance enhancements. Developers can now create embedded devices that are more compact and perform better to these enhancements.
- Enhancement of Nios V/g Core Performance increased effectiveness in completing tasks and enhanced overall performance
- Reduction of Nios V/c Core Area reduces the space by 8%, resulting in smaller designs.
- With the Ashling RISCFree IDE, Nios V program development is made easier with the help of the Visual Studio Code plugin.
- Developers can include machine learning (ML) capabilities into FPGA designs employing microcontrollers by using the TinyML Example Design with Nios V Application Note.
Features of Embedded Software
Strong OS and virtualisation support are essential for embedded applications based on FPGA. Quartus Prime Pro 25.1 enables developers to design scalable, real-time, and virtualised embedded systems by expanding compatibility for Linux, RTOS, and hypervisors.
- Reference Designs for Linux Hardware Regular and standard editions to ensure smooth Linux development.
- Developers can create virtualised environments for FPGA applications to support for the Xen hypervisor.
- Zephyr and Bare Metal are supported by RTOS, and FreeRTOS will be available in Q2 (May release).
Installer Enhancements: Quicker, More Adaptable Configuration
FPGA software should be easy to install and adaptable. Parallel processing, customisable component selection, and improved file management are some of the ways that Quartus Prime Pro 25.1 enhances the installation experience.
- Installation in Parallel enables the simultaneous installation of several components, cutting down on setup time.
- Selection of Dynamic Components reduces installation time and disc space by allowing users to select only the parts they require.
Streaming Debugging: Rapid Hardware Troubleshooting
The secret to cutting down on development cycles is efficient debugging. By enabling real-time, high-bandwidth data capture, the Streaming Debug IP for Signal Tap enhances engineers’ ability to examine and debug FPGA designs.
- Efficient data transfer for real-time analysis is made possible by high-speed streaming for hardware debugging.
- STP-based configurable streaming To set up the streaming technique and choose the right debug host, use Signal Tap Logic Analyser (STP).
Simulation Improvements
With the addition of new native Altera AXI4 Bus Functional Models (BFMs), Quartus Prime Pro 25.1 offers enhanced integration, long-term support, and simulation performance.
- Native Altera AXI4 BFMs are optimised for Quartus simulation workflows, guaranteeing improved performance and compatibility.
- Smooth Transition With closer toolchain integration, users can transition to the new Altera AXI4 BFMs without requiring major changes.
Significant simulation performance gains are brought about by Quartus Prime Pro 25.1, especially for transceiver protocol IP, which facilitates quicker and more effective debugging and verification.
- Better Protocol for Transceivers Support for PCIe, Ethernet, Serial Lite, JESD, and other transceiver protocols is improved via IP simulation.
- 25.1 Beta Models With an emphasis on Ethernet and PCIe, the new simulation models are now under beta testing for this version.
- Improved Efficiency Typically, improvements of 50% or more occur, speeding up verification and cutting down on simulation time.
By providing quicker, more effective simulations and cutting down on total verification time, these simulation enhancements enhance Quartus Prime Pro 25.1’s usefulness as a tool for transceiver-based FPGA designs.
Extra Quartus Prime Pro 25.1 Updates
Quartus Prime Design Suite (QPDS) Standard & Pro Containerised Images Docker Hub offers Quartus Prime Standard and Pro Editions in containerised form, which streamlines deployment and enhances compatibility with cloud and CI/CD processes.
- Summary of Design Closure makes it easier to classify the various failure kinds by separating timed closure data from Design Assistant outcomes.
- Reports’ SDC Relative File Paths enhances portability and streamlines script administration for Synopsys Design Constraints (SDC) reports.
- Improvements in MTBF (Mean Time Between Failure) When default toggle rates are not optimal, it allows users to fine-tune the toggle rate of individual instances to address MTBF issues.
Improvements to static timing analysis in Quartus Prime Pro 25.1 facilitate the efficient diagnosis and resolution of timing problems.
- Support for basic Quad-Port RAM in Synthesis Increases memory architecture versatility by enabling automatic inference of basic quad-port RAM.
- Complete Support for Byte Enable Inference in Synthesis: This expands support to accommodate 5, 8, 9, and 10-bit configurations, in line with full hardware capabilities, in addition to 8-bit byte enables.
- More Accurate Management In order to improve memory access and speed, users can now write individual bytes within a word using the byte enable control signal.
Designers may more easily utilise FPGA memory resources with improved RAM inference capabilities.
FPGA AI Suite: Increased Usability and AI Capabilities
FPGA-based inference systems must be more adaptable and effective as AI use grows. greater performance estimation, greater model support, and improved integration with Agilex FPGAs are all included in this edition.
- Agilex 3 Beta Support Agilex 3 FPGAs are now supported at the beta level by the FPGA AI Suite. The user can use Agilex 3 to build in Quartus and create Inference IP targeting Agilex 5 in the architectural configuration file.
- The RPM and DEB packages have been renamed to “altera-fpga-ai-suite-” and the AI Suite is now installed under “/opt/altera” rather than “/opt/intel” as well.
- High-accuracy object identification in robotics, surveillance, and industrial quality control applications is made possible with YoloV7 Model Support.
- Example Design Support for the Agilex 5 FPGA E-Series The Agilex 5 FPGA E-Series 065B Modular Development Kit now has new sample designs available.
- AI inference is demonstrated in this SoC example design using an ARM host CPU. AI Inference IP coupled with a new layout transform allows AI models to be optimised for better efficiency and usability by supporting folding and run-time configurability.
- Example of Hostless JTAG-Attach Design hostless design that enables users to configure and control IP functionality through a step-by-step, guided procedure using a system console that is attached to the Inference IP via JTAG.
- Memory Bandwidth Is Used by the Performance Estimator When designing for memory-limited devices like Agilex 5 and Agilex 3, users can now specify available external memory bandwidth, which improves accuracy compared to earlier versions.
- OpenVINO 2024.6 Integration To ensure stability and maintainability, FPGA AI Suite 25.1 switches to the most recent OpenVINO 2024.6 release.
- The Long-Term Support AI Suite, which makes use of fresh optimisations and performance enhancements, will only be available for Quartus Prime Pro editions for two years.
With improved speed, more extensive sample designs, and additional model support, FPGA AI Suite 25.1 facilitates the deployment of AI inference on FPGAs.
IP Features in Quartus Prime Pro 25.1
With the addition of additional Agilex 3 IP cores and significant Agilex 5 upgrades, Quartus Prime Pro 25.1 offers a wide range of applications real-time data processing, flexible memory access, and fast connection.
Agilex 3 IPs
A comprehensive collection of memory, processor, and connectivity IPs created for cost-effective applications is now included in Agilex 3:
- Adaptable I/O Assistance interfaces with high voltage and speed, such as 1.25 Gbps LVDS and MIPI D-PHY.
- PCIe 3.0, 10GE Hard IP, and 12.5Gbps transceivers provide dependable high-bandwidth applications.
- Economical Memory Support LPDDR4 for effective embedded memory solutions up to 2133 Mbps.
- ARM Cortex Integration Done Right Tight integration with ARM processors is guaranteed via HPS EMIF.
- High-Definition Image and Video Processing Applications for video and vision processing are accelerated by the VVP suite.
- JESD204B for Synchronising Data Converters allows for accurate 12.5Gbps multi-channel synchronisation.
- Using the Transceiver Toolkit for Advanced Debugging enhanced testing and debugging of transceiver links.
Updates for Agilex 5 IP
Performance and flexibility improvements are made to the Agilex 5 family IP, including:
- Adaptive Reconfiguration Modifications to several setups in real time using PMA-Direct
- PCIe 3.0/4.0 Multi-Channel DMA supports both Root Port (RP) and Endpoint (EP) modes for x2/x4 PCIe.
- 12.5 Gbps per serial lane in Interlaken made possible by the Agilex 5 D Series, which allowed for scalable data transfer.
- JESD204B at 17.16 Gbps with Transceiver Toolkit Advanced Debugging guarantees fast, accurate data flow.
- Protocol JESD204C in Dual-Simplex Mode enables more sophisticated signal processing by expanding high-speed ADC/DAC connectivity.
- O-RAN IP: Allows for real-time subcarrier spacing modifications via control messages and supports subcarrier frequencies ranging from 15 to 240 KHz.
Features for digital power scaling and conservation. - The enhanced performance, efficiency, and flexibility of the Agilex 3 and Agilex 5 FPGAs make them perfect for embedded, networking, and AI-driven applications.
Conclusion
Significant enhancements are made to Quartus Prime Pro 25.1 in the areas of Agilex 3 support, debugging tools, AI acceleration, IP cores, and general usability. This update improves performance, efficiency, and flexibility whether you’re optimising for embedded apps, high-speed interfaces, or AI workloads.
