Saturday, December 7, 2024

Unveiling the RISC-V Hardware Ecosystem

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RISC-V: why are we unlocking its potential?

What we’re investing in RISC-V for and why you should too

We’re founding members of a new project and firm to accelerate the RISC-V open-source ecosystem and platform.

RISC-V software enabling

At the end of May, Google, Intel, NXP, Nvidia, Red Hat, Samsung, and others established the RISC-V Software Ecosystem (RISE) Project to promote software adoption.

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Member funding and engineering of RISE Technical Steering Committee-aligned software deliverables. RISE will offer compilers, toolchains, system libraries, kernel, virtualization, programming languages, Linux distribution integration, firmware, and debug, profiling, emulation, and simulation tools for application processors.

Supporting RISC-V hardware

We invested in a startup with Robert Bosch, Infineon Technologies, Nordic Semiconductor, and NXP Semiconductors to speed RISC-V adoption.

The company will enable RISC-V products, provide reference architectures, and construct industry-standard solutions. Automotive will come first, then smartphones and IoT.

The company partners with key semiconductor firms to promote the RISC-V ecosystem and enable next-generation hardware development. The company requests industry associations, executives, and governments support this semiconductor ecosystem strengthening effort.

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What’s RISC-V?

Many OEMs and semiconductor manufacturers use RISC-V, the open standard instruction set architecture, to innovate, cut costs, and stay ahead.

RISC-V, meaning “risk five,” allows processor collaboration

Berkeley established the RISC-V standard in 2010 by establishing a simple, powerful ISA that anyone could use with few restrictions. The free, open-source ISA was released in 2015 to let anybody to develop, construct, and sell RISC-V processors without royalties or licence fees. This enabled various firms to design RISC-V processors and innovate in new product categories and applications.

ISA codebase can be edited and improved by architects, designers, and developers using open source. Teams can experiment with architectures and chip designs within the same ISA and share successes and failures.

Due to its flexibility and cost savings, RISC-V has expanded swiftly since it can adapt computing environments without proprietary ISAs.

Industries are realising these benefits and employing RISC-V cores for numerous applications, including:

AI image sensors

Maintain security

AI computing

5G network machine control and

Machine learning, graphics, and advanced storage

The 3 key RISC-V advantages

Flexibility: RISC-V lets users adapt and optimise software and hardware for specific use cases, faster development and optimising performance, power, and area tradeoffs.

RISC-V
image credit to Qualcomm

Control: Designers and developers can tweak their systems without third parties or architectural licences using an open ISA.

open-source nature of RISC-V allows developers additional codebase knowledge, making it easier to understand the roadmap and spot security risks early.

The full benefits of RISC-V

We interviewed Qualcomm Technologies Senior Vice President of Product Management Ziad Asghar about why RISC-V important to us and the value chain. He handles Qualcomm Technologies’ one technology roadmap for OEMs to create interoperable devices.

FC: Why is RISC-V improving?

Ziad Asghar (ZA): Legacy architectures are inflexible, hence an alternative was needed. The modern, adaptable, scalable, and open RISC-V architecture. RISC-V devices have demonstrated the ISA, and the ecosystem has noticed.

Qualcomm Technologies devices use RISC-V from 2019. OEMs making final products from it boost innovation. This progress solidifies the ecology, which the sector can support. Hopefully momentum will build.

FC: Why does Qualcomm want RISC-V?

ZA: RISC-V is promising. Product developers no longer need a proprietary ISA’s repertoire. It eliminates hefty licence payments for creating a new processor with a proprietary ISA. Any company can develop RISC-V CPUs without fees or royalties.

The nicest part is that product developers can tailor RISC-V to design for the end product. Openness, flexibility, and scalability attract us and other companies.

OEMs demand specialised cores for AI and ML development, hence RISC-V is growing. Indeed, RISC-V qualifies.

What are the finest RISC-V uses?

ZA: Most use cases benefit from RISC-V since you may optimise for unique use cases instead than choosing from a preset number of processor cores. You can optimise cores for power, performance, or area.

Custom RISC-V instructions are possible. You may then instruct AI and ML-like app improvements.

Finally, RISC-V encourages innovation and competition, benefiting consumers most. This openness allows difference, offering consumers a purer experience.

The openness of RISC-V benefits semiconductor makers, end devices, and customers.

How has Qualcomm employed RISC-V?

We invested in many RISC-V startups in 2019 and integrated their cores into our products. Since our device needed a control block, we integrated RISC-V microcontrollers for the Snapdragon 865 platform launch. We could design exactly what we wanted.

Qualcomm Technologies shipped 650 million RISC-V cores. Naturally, that number will climb.

Qualcomm Technologies‘ business strategy: where does this fit?

Starting with an open instruction set is intriguing for Qualcomm Technologies. Our best-in-class custom CPU team and RISC-V let us design, customise, and scale cores.

Our mobile, augmented reality, automotive, and internet of things firms use this strategy 24/7. 

We use less electricity and perform better with RISC-V. Consumers want speedier and longer-lasting electronics. All ecosystem members can differentiate more using RISC-V.

FC: How will RISC-V change? Will it become an ecosystem?

The flexibility and extension potential of RISC-V make it a good alternative to proprietary ISAs. Although traditional ISAs have plateaued, RISC-V is expanding rapidly. RISC-V’s open standard allows various corporations to integrate and optimise its cores, surpassing prior ISAs.

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