Friday, December 6, 2024

The new AMD FGPA based Alveo UL3524 accelerator card

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Alveo UL3524 accelerator card specifications

The AMD Alveo UL3524 accelerator card, a new fintech accelerator created for ultra-low latency electronic trading applications, is presently available for purchase. The Alveo UL3524 offers proprietary traders, market makers, hedge funds, brokerages, and exchanges a state-of-the-art FPGA platform for electronic trading at nanosecond (ns) speed. It has already been implemented by prominent trading businesses and enables different solution partner offerings.

The Alveo UL3524 achieves less than 3ns FPGA transceiver latency for quicker trade execution, a 7X increase in latency over preceding generation FPGA technology1. It uses a cutting-edge transceiver design with hardened, optimized network connection cores to provide breakthrough performance and is powered by a bespoke 16nm Virtex UltraScale+ FPGA. In comparison to conventional FPGA alternatives, the Alveo UL3524 allows quicker design closure and deployment by combining hardware flexibility with ultra-low latency networking on a production platform.

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Hamid Salehi, director of product marketing at AMD, said that “in ultra-low latency trading, a nanosecond can determine the difference between a profitable or losing trade.” “The Alveo UL3524 accelerator card is powered by the lowest latency FPGA transceiver from AMD purpose-built to give our fintech customers an unprecedented competitive advantage in the financial markets.”

Flexible Hardware and AI-Powered Trading Techniques

The Alveo UL3254 is equipped with 64 ultra-low latency transceivers, 780K LUTs of FPGA fabric, and 1,680 DSP slices of computation to speed bespoke trading algorithms in hardware, allowing traders to adapt their design to changing market circumstances and trading methods. The product is backed by global support from AMD domain experts and supported by conventional FPGA flows using Vivado Design Suite. It includes a suite of reference designs and performance benchmarks that let FPGA designers quickly explore key metrics and create custom trading strategies to specification.

AMD is offering developers the open-sourced and community-supported FINN programming platform to streamline the market’s growing usage of AI for algorithmic trading. The FINN project gives programmers the ability to use PyTorch and neural network quantization methods to shrink the size of AI models while maintaining accuracy, compile to hardware IP, and integrate the network model into the algorithm’s datapath for low latency performance. Being an open-source project, the solution offers developers freedom and access to the most recent developments as the projects progress.

Facilitating the Development of an Ecosystem of Ultra-Low Latency Fintech Solutions

Strategic partners are able to create specialized solutions and infrastructure for the financial business thanks to the Alveo UL3524 and purpose-built FPGA technology. Partner solutions from Alpha Data, Exegy, and Hypertec are now on the market.

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The Alveo UL3524 accelerator card, powered by the AMD Virtex UltraScale+ VU2P FPGA, enables Alpha Data’s ultra-low latency appliances.

According to David Miller, managing director of Alpha Data, “the new Virtex UltraScale+ FPGA from AMD brings a step change to ultra-low latency trading and networking.” AMD created the ADA-R9100 rack-mount appliance so that users may readily utilize the new AMD FPGA device’s full capability.

The Alveo UL3524 card is supported by Exegy, a supplier of complete front-office trading solutions, with the aid of its nxFramework, a software and hardware development environment designed specifically for building and maintaining ultra-low latency FPGA applications for the financial sector.  

“We’re able to deliver a comprehensive solution that addresses the ever-increasing optimization needed to build the trading infrastructure of tomorrow by combining the cutting-edge ultra-low latency FPGA technology from AMD with Exegy’s expertise in capital markets,” said Olivier Cousin, director of FPGA solutions at Exegy.

To deploy in a 1U server form factor, Hypertec has customized its ORION HF X410R-G6 High Frequency Server for the Alveo UL3524.  

“The engineers at Hypertec specifically designed the HF X410R-G6 to extract the best out of the capabilities and speed of the Alveo UL3524 platform, catering our solution to the most demanding low-latency tasks,” said David Lim, director of product marketing at Hypertec.

Customers in the worldwide financial services industry are now receiving AMD Alveo UL3524 accelerator cards that are currently in production.

Regarding AMD

AMD has been a pioneer in the development of high-performance computing, graphics, and visualization technologies for more than 50 years. AMD technology is used on a daily basis by billions of people, top Fortune 500 companies, and cutting-edge scientific research facilities all around the globe to enhance how they live, work, and play. Building adaptable, high-performance solutions that push the envelope of what is possible is a top priority for AMD personnel.

Virtex, Vivado, Alveo, and the AMD Arrow logo are all trademarks of Advanced Micro Devices, Inc. Other names are included simply for informative reasons; they can be trademarks belonging to their respective owners.

Alveo UL3524 accelerator card testing performed by AMD Performance Labs as of 8/16/23 utilizing Vivado Design Suite 2023.1 and Vivado Lab (Hardware Manager) 2023.1. GTF transceivers may be used in internal near-end loopback mode thanks to a design that is based on the GTF Latency Benchmark. The GTF TX and RX clocks have a 180 degree phase shift and run at the same frequency of around 64 MHz.

By latching the value of a single free running counter, the GTF Latency Benchmark Design gauges latency in hardware. When TX data is latched at the GTF transceiver and when TX data is latched at the GTF receiver before being sent back into the FPGA fabric, that is the difference in latency. Protocol overhead, protocol framing, programmable logic (PL) delay, TX PL interface setup time, RX PL interface clock-to-out, package flight time, and other types of latency are not taken into account when measuring latency.

A 250-frame benchmark test was performed 1,000 times. Citation of measurement results is based on GTF transceiver “RAW Mode,” in which the transceiver’s PCS (physical medium attachment) transmits data to the FPGA fabric “as-is.” All test runs for this setup measure latency consistently. System makers may change settings, producing various outcomes. ALV-10

 based on a simulated comparison of ultra-low latency GTF transceivers with Virtex UltraScale+ GTY transceivers.

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agarapuramesh
agarapurameshhttps://govindhtech.com
Agarapu Ramesh was founder of the Govindhtech and Computer Hardware enthusiast. He interested in writing Technews articles. Working as an Editor of Govindhtech for one Year and previously working as a Computer Assembling Technician in G Traders from 2018 in India. His Education Qualification MSc.
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